Parallel Computing

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Research

Research in the parallel computing group is focused on solving compute and memory intensive problems in high speed network processing, data intensive computing and high performance computing. Examples are virtualized packet classification and deep packet inspection for the Internet backbone, large-scale pattern matching, belief propagation and graph inference. We investigate new algorithms and algorithm-architecture mapping to optimize our solutions on parallel and/or heterogeneous architectures including Field-Programmable Gate Arrays (FPGA), general purpose multi-core (CPU) and graphics (GPU) processors.

  • Research Areas
    • Virtualized router architecture
    • Traffic classification
    • High performance, multi-field packet classification
    • Deep packet inspection
    • Parallelism for machine learning
    • Parallelization on cloud platform
  • Current Projects
    • High-performance Data Plane Kernels for Software Defined Networking
    • Accelerating Large Scale Pattern Matching for Data Intensive Applications
    • Parameterized and Tunable Linear Algebra Library for FPGA-Accelerated Systems
    • Hardware-Software Co-Design for Next Generation Packet Forwarding Engines
    • TAPAS: Tunable Algorithms for PERFECT Architectures

Publications

  • Recent publications
  1. Shijie Zhou and Viktor K. Prasanna, Scalable GPU-Accelerated IPv6 Lookup using Hierarchical Perfect Hashing, 2015 IEEE Global Communications Conference (GLOBECOM '15), December 2015
  2. Ren Chen and Viktor K. Prasanna, Automatic Generation of High Throughput Energy Efficient Streaming Architectures for Arbitrary Fixed Permutations, IEEE International Conference on Field-programmable Logic and Applications (FPL '15), September 2015
  3. Yun R. Qu and Viktor K. Prasanna, Power-efficient Range-match-based Packet Classification on FPGA, IEEE International Conference on Field-programmable Logic and Applications (FPL), September 2015
  4. Ren Chen, Shreyas Singapura and Viktor K. Prasanna, Optimal Dynamic Data Layouts for 2D FFT on 3D Memory Integrated FPGA, International Conference on Parallel Computing Technologies (PaCT '15), August 2015
  5. Shijie Zhou, Yun R. Qu, and Viktor K. Prasanna, Large-scale Packet Classification on FPGA, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP '15), July 2015
  6. Shijie Zhou, Charalampos Chelmis, and Viktor K. Prasanna, Accelerating Large-Scale Single-Source Shortest Path on FPGA, Reconfigurable Architectures Workshop (RAW '15), May 2015
  7. Da Tong, Shijie Zhou, and Viktor K. Prasanna, High Throughput Online Hash Table on FPGA, Reconfigurable Architectures Workshop (RAW '15), May 2015
  8. Yun R. Qu, Hao H. Zhang, Shijie Zhou, Vikor K. Prasanna, Optimizing Many-field Packet Classification on FPGA, multi-core General Purpose Processor, and GPU, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), May 2015
  9. Yun R. Qu and Viktor K. Prasanna, Enabling High Throughput and Virtualization for Traffic Classification on FPGA, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2015
  10. Shreyas G. Singapura, Anand Panangadan, and Viktor K. Prasanna, Performance Modeling of Matrix Multiplication on 3D Memory Integrated FPGA, 22nd Reconfigurable Architectures Workshop (RAW), 29th Annual International Parallel & Distributed Processing Symposium (IPDPS), Hyderabad, India, May 2015
  11. Shreyas G. Singapura, Anand Panangadan, and Viktor K. Prasanna, Towards Performance Modeling of 3D Memory Integrated FPGA Architectures, 11th International Symposium on Applied Reconfigurable Computing (ARC '15), April 2015
  12. Ren Chen and Viktor K. Prasanna, DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-based Systems, 11th International Symposium on Applied Reconfigurable Computing (ARC '15), April 2015
  13. Ren Chen and Viktor K. Prasanna, Energy and Memory Efficient Bitonic Sorting on FPGA, ACM/SIGDA International Conference on Field-Programmable Gate Arrays (FPGA '15), February 2015
  14. Sanmukh R. Kuppannagari and Viktor K. Prasanna, Efficient Generation of Energy and Performance Pareto Front for FPGA Designs, ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '15), February 2015
  15. Yun R. Qu and Viktor K. Prasanna, High-performance and Dynamically Updatable Packet Classification Engine on FPGA, IEEE Transactions on Parallel and Distributed Systems (TPDS), December 2014
  16. Yun R. Qu, Shijie Zhou and Viktor K. Prasanna, A Decomposition-based Approach for Scalable Many-field Packet Classification on Multi-core Processors, International Journal of Parallel Programming (IJPP), December 2014
  17. Vaibhav R. Gandhi, Yun R. Qu and Viktor K. Prasanna, High-Throughput Hash-based Online Traffic Classification Engines on FPGA, IEEE International Conference on Reconfigurable Computing and FPGAs (ReConfig '14), December 2014
  18. Andrea Sanny, Yi-Hua E. Yang and Viktor K. Prasanna, Energy-Efficient Histogram on FPGA, IEEE International Conference on Reconfigurable Computing and FPGAs (ReConfig '14), December 2014
  19. Shijie Zhou, Sihan Zhao and Viktor K. Prasanna, 400 Gbps Energy-Efficient Multi-Field Packet Classification on FPGA, 2014 IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig '14), December 2014
  20. Shijie Zhou, Weirong Jiang and Viktor K. Prasanna, A Flexible and Scalable High-Performance OpenFlow Switch on Heterogeneous SoC Platforms, International Performance, Computing, and Communications Conference (IPCCC '14), December 2014
  21. Ren Chen and Viktor K. Prasanna, Algorithmic Optimizations for Energy-efficient Throughput-oriented FFT architecture, IEEE Green Computing Conference (IGCC '14), November 2014
  22. Sanmukh R. Kuppannagari, Yusong Hu and Viktor Prasanna, High Level Performance Model Based Design Space Exploration for Energy-Efficient Designs on FPGAs, IEEE 5th International Green Computing Conference (IGCC '14), November 2014
  23. Yun Qu and Viktor Prasanna, Compact Hash Tables for High-performance Traffic Classification on Multi-core Processors, IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '14), October 2014
  24. Shijie Zhou, Prashant Rao Nittoor and Viktor Prasanna, High-Performance Traffic Classification on GPU, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '14), October 2014
  25. Ren Chen and Viktor Prasanna, Energy Optimizations for FPGA-based 2-D FFT Architecture, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  26. Sanmukh R. Kuppannagari, Shreyas G. Singapura, Ren Chen, Andrea Sanny, Geoffrey Phi C. Tran, Shijie Zhou, Yusong Hu, Stephen P. Crago, Viktor K. Prasanna, Energy Performance of FPGAs on PERFECT Suite Kernels, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  27. Andrea Sanny and Viktor Prasanna, Energy-Efficient Histogram Equalization on FPGA, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  28. Yun Qu and Viktor Prasanna, Scalable and Dynamically Updatable Lookup Engine for Decision-trees on FPGA, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  29. Shijie Zhou, Shreyas G. Singapura and Viktor K. Prasanna, High-Performance Packet Classification on GPU, IEEE 18th International Conference on High Performance Extreme Computing (HPEC '14), September 2014
  30. Shijie Zhou, Weirong Jiang and Viktor K. Prasanna, A Programmable and Scalable OpenFlow Switch using Heterogeneous SoC Platforms, ACM SIGCOMM Workshop on Hot Topics in Software Defined Networking (HotSDN '14), August 2014
  31. Yun Qu, Shijie Zhou and Viktor Prasanna, Performance Modeling and Optimizations for Decomposition-based Large-scale Packet Classification on Multi-core Processors, IEEE 15th International Conference on High Performance Switching and Routing(HPSR '14), July 2014
  32. Da Tong, Yun Qu and Viktor Prasanna, High-throughput Traffic Classification on Multi-core Processors, IEEE 15th International Conference on High Performance Switching and Routing(HPSR '14), July 2014
  33. Ren Chen and Viktor K. Prasanna, Energy-Efficient Architecture for Permutation on Streaming Data, Ph.D forum on IEEE Parallel & Distributed Processing Symposium (IPDPS '14), May 2014
  34. Da Tong and Viktor Prasanna, Online heavy hitter detector on FPGA, 2013 IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig '13), December 2013
  35. Da Tong and Viktor Prasanna, Dynamically Configurable Online Statistical Flow Feature Extractor on FPGA, 2013 IEEE International Conference on High Performance Extreme Computing (HPEC '13), September 2013
  36. Da Tong, Lu Sun, Kiran Matam and Viktor Prasanna High Throughput and Programmable Online Traffic Classifier on FPGA, 2013 the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '13), February 2013
  37. Andrea Sanny and Viktor K. Prasanna, Energy-Efficient Median Filter on FPGA, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  38. Kiran Kumar Matam and Viktor K. Prasanna, Energy-Efficient Large-Scale Matrix Multiplication on FPGAs, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  39. Kiran Kumar Matam, Hoang Le and Viktor K. Prasanna, Evaluating Energy Efficiency of Floating Point Matrix Multiplication on FPGAs, IEEE High Performance Extreme Computing Conference (HPEC '13), September 2013
  40. Kiran Kumar Matam, Hoang Le and Viktor K. Prasanna, Energy Efficient Architecture for Matrix Multiplication on FPGAs, IEEE International Conference on Field Programmable Logic and Applications (FPL '13), August 2013
  41. Kiran Kumar Matam and Viktor K. Prasanna, Algorithm Design Methodology for Embedded Architectures, International Symposium on Applied Reconfigurable Computing (ARC '13), March 2013
  42. Thilan Ganegedara and Viktor K. Prasanna, 100+ Gbps IPv6 Packet Forwarding on Multi-Core Platforms, 2013 IEEE Global Communications Conference (GLOBECOM '13), December 2013 (Best Paper Award)
  43. Ren Chen and Viktor K. Prasanna, Energy-Efficient Architecture for Stride Permutation on Streaming Data, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  44. Ren Chen, Neungsoo Park and Viktor K. Prasanna, High Throughput Energy Efficient Parallel FFT Architecture on FPGAs, IEEE High Performance Extreme Computing Conference (HPEC '13), September 2013
  45. Ren Chen, Hoang Le and Viktor K. Prasanna, Energy Efficient Parameterized FFT Architecture, IEEE International Conference on Field Programmable Logic and Applications (FPL '13), August 2013
  46. Yun Qu, Shijie Zhou and Viktor Prasanna, Scalable Many-field Packet Classification on Multi-core Processors, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '13), October 2013
  47. Yun Qu, Shijie Zhou and Viktor Prasanna, High-performance Architecture for Dynamically Updatable Packet Classification on FPGA, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '13), October 2013
  48. Shijie Zhou, Yun Qu and Viktor Prasanna, Multi-core Implementation of Decomposition-based Packet Classification Algorithms, International Conference on Parallel Computing Techniques (PaCT '13), September 2013
  49. Yi-Hua E. Yang, Yun Qu, Swapnil Haria and Viktor Prasanna, Architecture and Performance Models for Scalable IP Lookup Engines on FPGA, International Conference on High Performance Switching and Routing (HPSR '13), June 2013
  50. Yun Qu and Viktor Prasanna, Fast Dynamically Updatable Packet Classifier on FPGA, International Conference on Field Programmable Logic and Applications (FPL '13), May 2013
  51. Yun Qu and Viktor Prasanna, High-performance Pipelined Architecture for Tree-based IP lookup Engine on FPGA, Reconfigurable Architectures Workshop (RAW '13), January 2013
  52. Andrea Sanny, Thilan Ganegedara and Viktor Prasanna, A Comparison of Ruleset Feature Independent Packet Classification Engines on FPGA, Reconfigurable Architectures Workshop (RAW '13), January 2013
  53. Da Tong, Yi-Hua Yang and Viktor Prasanna, A Memory Efficient IPv6 Lookup Engine on FPGA, 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig '12), December 2012
  54. Swapnil Haria, Thilan Ganegedara and Viktor Prasanna, Power Efficient and Scalable Virtual Routers on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig '12), December 2012
  55. Nam Ma, Yinglong Xia and Viktor Prasanna, Parallel Exact Inference on Multicore Using MapReduce, 24rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '12), October 2012
  56. Weirong Jiang and Viktor K. Prasanna, Scalable Packet Classification on FPGA, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), September 2012
  57. Thilan Ganegedara, Viktor Prasanna and Gordon Brebner, Optimizing Packet Lookup in Time and Space on FPGA, 22nd International Conference on Field Programmable Logic and Applications (FPL '12), August 2012
  58. Yi-Hua E. Yang and Viktor K. Prasanna, High-Performance and Compact Architecture for Regular Expression Matching on FPGA, IEEE Transactions on Computers, July 2012
  59. Yi-Hua E. Yang and Viktor K. Prasanna, Robust and Scalable String Pattern Matching for Deep Packet Inspection on Multi-core Processors, Source Code, IEEE Trans. on Distributed and Parallel Symposium (TDPS), July 2012
  60. Hoang Le and Viktor K. Prasanna, Scalable Tree-based Architectures for IPv4/v6 Lookup Using Prefix Partitioning, IEEE Transactions on Computers, July 2012
  61. Thilan Ganegedara and Viktor Prasanna, StrideBV: Single Chip 400G+ Packet Classification, 13th Conference on High Performance Switching and Routing (HPSR '12), June 2012 (Best Paper Award)
  62. Yun Qu, Yi-Hua E. Yang and Viktor Prasanna, Large-scale Multi-flow Regular Expression Matching on FPGA, 13th Conference on High Performance Switching and Routing (HPSR '12), June 2012
  63. Thilan Ganegedara and Viktor Prasanna, FPGA-based Router Virtualization: A Power Perspective, The 19th Reconfigurable Architectures Workshop (RAW '12), May 2012 (Selected as one of five best papers)
  64. Nam Ma, Yinglong Xia and Viktor Prasanna, Task Parallel Implementation of Belief Propagation in Factor Graphs, Workshop on Parallel and Distributed Computing for Machine Learning and Inference Problems (ParLearning’12 - in conjunction with IPDPS '12), May 2012
  65. Weirong Jiang and Viktor K. Prasanna, Data Structure Optimization for Power-Efficient IP Lookup Architectures, IEEE Transactions on Computers, 2012
  66. Yinglong Xia and Viktor K. Prasanna, Distributed Evidence Propagation in Junction Trees on Clusters, IEEE Transactions on Parallel and Distributed Systems, July 2012
  67. Hoang Le and Viktor K. Prasanna, A Memory-Efficient and Modular Approach for Large-Scale String Pattern Matching, IEEE Transctions on Computers, February 2012
  68. Yun Qu, Yi-Hua E. Yang and Viktor K. Prasanna, Multi-stream Regular Expression Matching on FPGA, 2011 International Conference on ReConFigurable Computing and FPGAs (ReConFig '11), December 2011
  69. Lu Sun, Hoang Le and Viktor K. Prasanna, Optimizing Decomposition-based Packet Classification Implementation on FPGAs, 2011 International Conference on ReConFigurable Computing and FPGAs (ReConFig '11), December 2011 (Best Paper Award Nomination)

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