Parallel Computing

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Research

Research in the parallel computing group is focused on solving compute and memory intensive problems in high speed network processing, data intensive computing and high performance computing. Examples are virtualized packet classification and deep packet inspection for the Internet backbone, large-scale pattern matching, belief propagation and graph inference. We investigate new algorithms and algorithm-architecture mapping to optimize our solutions on parallel and/or heterogeneous architectures including Field-Programmable Gate Arrays (FPGA), general purpose multi-core (CPU) and graphics (GPU) processors.

  • Research Areas
    • Virtualized router architecture
    • Traffic classification
    • High performance, multi-field packet classification
    • Deep packet inspection
    • Parallelism for machine learning
    • Parallelization on cloud platform
  • Current Projects
    • High-performance Data Plane Kernels for Software Defined Networking
    • Accelerating Large Scale Pattern Matching for Data Intensive Applications
    • Parameterized and Tunable Linear Algebra Library for FPGA-Accelerated Systems
    • Hardware-Software Co-Design for Next Generation Packet Forwarding Engines
    • TAPAS: Tunable Algorithms for PERFECT Architectures

Publications

  • Recent publications
  1. Da Tong and Viktor Prasanna, Online heavy hitter detector on FPGA, 2013 IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig '13), December 2013
  2. Da Tong and Viktor Prasanna, Dynamically configurable online statistical flow feature extractor on FPGA, 2013 IEEE International Conference on High Performance Extreme Computing (HPEC '2013), September 2013
  3. Da Tong; Lu Sun; Kiran Matam; Viktor Prasanna High throughput and programmable online traffic classifier on FPGA, 2013 the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '13), February 2013
  4. Andrea Sanny and Viktor K. Prasanna, Energy-Efficient Median Filter on FPGA, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  5. Kiran Kumar Matam and Viktor K. Prasanna, Energy-Efficient Large-Scale Matrix Multiplication on FPGAs, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  6. Kiran Kumar Matam, Hoang Le, and Viktor K. Prasanna, Evaluating Energy Efficiency of Floating Point Matrix Multiplication on FPGAs, IEEE High Performance Extreme Computing Conference (HPEC '13), September 2013
  7. Kiran Kumar Matam, Hoang Le, and Viktor K. Prasanna, Energy Efficient Architecture for Matrix Multiplication on FPGAs, IEEE International Conference on Field Programmable Logic and Applications (FPL '13), August 2013
  8. Kiran Kumar Matam and Viktor K. Prasanna, Algorithm Design Methodology for Embedded Architectures, International Symposium on Applied Reconfigurable Computing (ARC '13), March 2013
  9. Ren Chen and Viktor K. Prasanna, Energy-Efficient Architecture for Stride Permutation on Streaming Data, IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig '13), December 2013
  10. Ren Chen, Neungsoo Park and Viktor K. Prasanna, High Throughput Energy Efficient Parallel FFT Architecture on FPGAs, IEEE High Performance Extreme Computing Conference (HPEC '13), September 2013
  11. Ren Chen, Hoang Le and Viktor K. Prasanna, Energy Efficient Parameterized FFT Architecture, IEEE International Conference on Field Programmable Logic and Applications (FPL '13), August 2013
  12. Yun Qu, Shijie Zhou, Viktor Prasanna, Scalable Many-field Packet Classification on Multi-core Processors, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD ’13), October 2013
  13. Yun Qu, Shijie Zhou, Viktor Prasanna, High-performance Architecture for Dynamically Updatable Packet Classification on FPGA, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS ’13), October 2013
  14. Shijie Zhou, Yun Qu, Viktor Prasanna, Multi-core Implementation of Decomposition-based Packet Classification Algorithms, International Conference on Parallel Computing Techniques (PaCT ’13), September 2013
  15. Yi-Hua E. Yang, Yun Qu, Swapnil Haria, Viktor Prasanna, Architecture and Performance Models for Scalable IP Lookup Engines on FPGA, International Conference on High Performance Switching and Routing (HPSR ’13), June 2013
  16. Yun QU, Viktor Prasanna, Fast Dynamically Updatable Packet Classifier on FPGA, International Conference on Field Programmable Logic and Applications (FPL ’13), May 2013
  17. Yun QU, Viktor Prasanna, High-performance Pipelined Architecture for Tree-based IP lookup Engine on FPGA, Reconfigurable Architectures Workshop (RAW ’13), January 2013
  18. Andrea Sanny, Thilan Ganegedara, Viktor Prasanna, A Comparison of Ruleset Feature Independent Packet Classification Engines on FPGA, Reconfigurable Architectures Workshop (RAW ’13), January 2013
  19. Da Tong, Yi-Hua Yang, and Viktor Prasanna, A memory efficient IPv6 lookup engine on FPGA, 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig '12)
  20. Swapnil Haria, Thilan Ganegedara, Viktor Prasanna, Power Efficient and Scalable Virtual Routers on FPGA, International Conference on ReConFigurable Computing and FPGAs (ReConFig'12), December 2012
  21. Nam Ma, Yinglong Xia, Viktor Prasanna, Parallel Exact Inference on Multicore Using MapReduce, 24rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'12), October 2012.
  22. Weirong Jiang and Viktor K. Prasanna, Scalable Packet Classification on FPGA, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), September 2012.
  23. Thilan Ganegedara, Viktor Prasanna, Gordon Brebner, Optimizing Packet Lookup in Time and Space on FPGA, 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), August 2012.
  24. Yi-Hua E. Yang and Viktor K. Prasanna, High-Performance and Compact Architecture for Regular Expression Matching on FPGA, IEEE Transactions on Computers, July 2012.
  25. Yi-Hua E. Yang and Viktor K. Prasanna, Robust and Scalable String Pattern Matching for Deep Packet Inspection on Multi-core Processors, Source Code, IEEE Trans. on Distributed and Parallel Symposium (TDPS), July 2012.
  26. Hoang Le and Viktor K. Prasanna, Scalable Tree-based Architectures for IPv4/v6 Lookup Using Prefix Partitioning, IEEE Transactions on Computers, July 2012.
  27. Thilan Ganegedara, Viktor Prasanna, StrideBV: Single Chip 400G+ Packet Classification, 13th Conference on High Performance Switching and Routing (HPSR 2012), June 2012.(Best Paper Award)
  28. Yun Qu, Yi-Hua E. Yang, Viktor Prasanna, Large-scale multi-flow regular expression matching on FPGA, 13th Conference on High Performance Switching and Routing (HPSR 2012), June 2012.
  29. Thilan Ganegedara, Viktor Prasanna, FPGA-based Router Virtualization: A Power Perspective, The 19th Reconfigurable Architectures Workshop (RAW 2012), May 2012. (Selected as one of five best papers)
  30. Nam Ma, Yinglong Xia, Viktor Prasanna, Task Parallel Implementation of Belief Propagation in Factor Graphs, Workshop on Parallel and Distributed Computing for Machine Learning and Inference Problems (ParLearning’12 - in conjunction with IPDPS'12), May 2012.
  31. Weirong Jiang and Viktor K. Prasanna, Data Structure Optimization for Power-Efficient IP Lookup Architectures, IEEE Transactions on Computers, 2012.
  32. Yinglong Xia and Viktor K. Prasanna, Distributed Evidence Propagation in Junction Trees on Clusters, IEEE Transactions on Parallel and Distributed Systems, July 2012.
  33. Hoang Le and Viktor K. Prasanna, A Memory-Efficient and Modular Approach for Large-Scale String Pattern Matching, IEEE Transctions on Computers, February 2012.
  34. Yun Qu, Yi-Hua E. Yang and Viktor K. Prasanna, Multi-stream Regular Expression Matching on FPGA, 2011 International Conference on ReConFigurable Computing and FPGAs (ReConFig '11), December 2011.
  35. Lu Sun, Hoang Le and Viktor K. Prasanna, Optimizing Decomposition-based Packet Classification Implementation on FPGAs, 2011 International Conference on ReConFigurable Computing and FPGAs (ReConFig '11), December 2011. (Best Paper Award Nomination)

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